← 返回 JSSC 论文列表JSSC 2021第11期Power Management130nm CMOSPLLVCO
A 23 GHz 28 mW Sampling PLL Achieving 110 dBcHz In-Band Phase Noise and 500 MHz
一种无相位插值器的23 GHz采样锁相环，实现110 dBc/Hz带内相位噪声和500 MHz FMCW啁啾。
23 GHz, 28 mW, 110 dBc/Hz带内相位噪声, 500 MHz FMCW啁啾, 1.2V电源
采样锁相环线性斜率发生器相位噪声FMCW啁啾分数分频
▸无相位插值器（PI）或数字时间转换器（DTC）
▸采用线性斜率发生器（LSG）直接采样相位误差
▸3位DAC相位插值电荷泵（PICP）实现分数分频
Abstract
A phase interpolator (PI)-free fractional- N sam-
pling phase-locked loop (SPLL) has been proposed and
implemented in 130 nm CMOS technology, which eliminates
time-domain PI, digital-to-time converter (DTC), or background
calibration. This phase-locked loop (PLL) employs two linear
slope generators (LSGs) to produce linear waveforms, which
are related to the VCO feedback phase. Then the reference
directly samples the LSG outputs to obtain the phase error.
Following this, a 3 bit DAC-based phase