JSSC 2021第11期Data Converters28nmPLL

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL Jianglin Du

提出一种采用参考波形过采样技术的低功耗分数N ADPLL，有效降低抖动和建立时间。

2.0–2.3-GHz, 414 fs rms jitter, 1.15 mW, -247 dB FoM

分数N ADPLL参考波形过采样低功耗相位检测器LMS校准

▸创新点1：参考波形过采样（ROS）相位检测器，通过四倍过采样率显著降低抖动和锁定时间，提升了系统性能。

▸创新点2：底部板采样与电压零强制技术，结合可编程DAC实现高效电压域分数相位补偿，提高了功率效率。

▸创新点3：LMS算法校准增益失配，有效降低分数杂散，提升了系统的频率稳定性和精度。

▸创新点4：低噪声门控放大器和低功耗SAR-ADC的应用，进一步降低了系统噪声和功耗，实现了高性能与低功耗的平衡。

Abstract

This article presents a low-power fractional- N all- digital phase-locked loop (ADPLL) employing a reference- waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter and set- tling time. The proposed ROS-PD adopts a bottom-plate sampling with a voltage zero-forcing technique, which yields high power efﬁciency and supports fractional phase compensation in the voltage domain through a programmable DAC. The PD output is then ampliﬁe