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JSSC 2021第11期Digital Circuits28nm

On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine

通过低摆幅调谐实现能效与信号质量权衡的片上链路设计
28nm CMOS, 能效提升5.1倍
片上链路能效优化机器学习计算机视觉低摆幅
创新点1:低摆幅调谐技术(方法创新) - 通过动态调整信号摆幅实现能量与信号质量的灵活权衡,在28nm CMOS工艺下实现最高5.1倍的能量节省,同时支持机器学习等容错应用的渐进式质量降级。
创新点2:子字排序与非均匀摆幅分配(系统创新) - 针对数据重要性差异提出分级处理机制,对关键子字保留高摆幅而次要子字采用低摆幅,在AlexNet等神经网络中验证了能量效率与计算精度的协同优化。
创新点3:局部变化优化的摆幅选择(电路创新) - 开发自适应电路实时监测工艺/电压/温度变化,动态选择最优摆幅配置,在3200个链路测试中显著降低能量波动性(ISO-quality条件下优于传统近似计算链路)。
创新点4:兼容性设计(系统创新) - 保留传统收发器接口实现无缝集成,在标准CMOS工艺下达到与先进工艺专用电路相当的最低能耗(0.89pJ/bit),支持全精度模式与近似模式的动态切换。
Abstract
This article presents a class of on-chip links that reduce energy at graceful signal quality degradation via low-swing tuning, leveraging the error resilience of prominent applications (e.g., machine learning, vision). To mitigate the expo- nential quality degradation at low swings, sub-word ranking and non-uniform swing allocation are introduced. An efficient swing selection to exploit local variations is presented. The proposed links also outperform approximate links in terms of energy and its variability at ISO-quality, while allowing full-quality execution when needed. The proposed techniques are demonstrated in a 28-nm testchip with differential and voltage-scaled standard CMOS links. Results on 20 dies and 3200 links under neural network (LeNet-5 and AlexNet) and computer vision workloads show that the energy can be reduced by up to 5.1X on average across 20 dies, compared with a conventionally designed link. When reusing conventional transmitter and receiver for easy integration, the minimum energy is comparable with prior best- in-class links using more advanced CMOS technologies and dedicated circuit techniques.