← 返回 JSSC 论文列表JSSC 2021第12期Clocking & PLLs14nm FINFETPLL
A 14-nm Ultra-Low Jitter Fractional- N PLL Using a DTC Range Reduction Technique
14nm工艺下采用DTC范围缩减技术的超低抖动分数N锁相环
6GHz, 83.4fs抖动(10k-100MHz), -250.1dB FoM, 14.2mW
分数N锁相环数字时间转换器相位噪声可重构VCO背景校准
▸DTC范围缩减技术降低热噪声并提高线性度
▸可重构双核VCO优化功耗与抖动平衡
▸数字背景校准保持宽频带内抖动稳定
Abstract
This work presents a 6-GHz low-jitter and high
figure-of-merit (FoM) fractional- N phase-locked loop (PLL).
It uses a digital-to-time conv erter (DTC)-based sampling PLL
architecture. To achieve ultra-low jitter in fractional- N mode,
a phase detector range reduction technique is used to halve the
required DTC delay range (DR), resulting in lower thermal noise
and better DTC linearity. Moreover, a reconfigurable dual-core
voltage-controlled oscillator (VCO) provides extra freedom in
power and jitt