A 14-nm Ultra-Low Jitter Fractional- N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Abstract

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- N phase-locked loop (PLL). It uses a digital-to-time conv erter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional- N mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional-N mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from −250.1 to −251.2 dB, as the PLL power con- sumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than −70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5–7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm 2.