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A 32-kHz-Reference 24-GHz Fractional- N Oversampling PLL With 200-kHz Loop Bandw
提出一种基于32kHz参考的2.4GHz分数N过采样锁相环，采用混合信号设计，实现低抖动和低杂散。
65nm CMOS, 1V, 4.97mW, 5.79ps rms抖动, -36dBc分数杂散, -78dBc参考杂散
锁相环过采样分数N抖动杂散
▸利用电压和时间域信息实现过采样相位检测
▸采用DAC和DTC构建反馈信号并提高分辨率
▸基于自适应查找表的校准方法优化DAC和DTC控制
Abstract
In this article, a mixed–signal, 32-kHz reference-
based 2.4-GHz fractional- N over-sampling phase-locked loop
(OSPLL) is proposed. Different from the conventional 1 × sam-
pling PLL, which only uses zero-crossing timing information of
the reference signal, the proposed OSPLL fully utilizes both the
voltage and timing domain information of the reference signal
and realizes oversampling ratio (OSR) times phase detection (PD)
in one reference cycle. The proposed OSPLL employs the digital-
to-analo