JSSC 2022第1期Wireline I/O7nm FinFETEqualizerPAM-4

A 112-Gbs PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline R

本文提出了一种低功耗九抽头滑动块决策反馈均衡器（SB-DFE），用于112Gb/s PAM-4长距离有线接收器，采用7nm FinFET工艺。

112Gb/s PAM-4, 7nm FinFET, 36dB损耗通道, 误码率2×10^-12, 功耗降低0.33pJ/b

决策反馈均衡器滑动块架构PAM-4长距离有线接收器7nm FinFET

▸采用滑动块架构（SB-DFE），克服传统DFE的实现挑战

▸支持多达30抽头的DFE实现，且计算开销可任意小

▸优化流水线切割以最小化延迟，同时保持时序裕度

Abstract

Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to signiﬁcant power, area, and timing costs. This arti cle presents a systolic many- tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of con- ventional DFEs with no performance loss. A nine-tap conﬁgu- ration is demonstrated in a 112-Gb/s analog-to-digital converter (ADC)-d