A 40-nm, 64-Kb, 56.67 TOPS/W V oltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With V erification and Online Read-Dis turb Detection Jong-Hyeok Y oon , Member , IEEE

Abstract

Computing-in-memory (CIM) architectures have gained importance in achieving high-throughput energy-efficient artificial intelligence (AI) systems. Resistive RAM (RRAM) is a promising candidate for CIM architectures due to a multiply- and-accumulate (MAC)-friendly s tructure, high bit density, compatibility with a CMOS process, and nonvolatility. Notwith- standing the advancement of RRAM technology, the reliability of an RRAM array hinders the spread of RRAM applications such that a circuit-technology joint approach is necessary to attain reliable RRAM-based CIM architectures. This article presents a 64-kb hybrid CIM/digital RRAM macro supporting: 1) active- feedback-based voltage-sensing read (RD) to enable 1–8-b pro- grammable vector-matrix multiplication under a low-resistance ratio of the high-resistance state to the low-resistance state in an RRAM array; 2) iterative write with verification to secure a tight resistance distribution; and 3) online RD-disturb detection in the background during CIM. The test chip fabricated in a 40-nm CMOS and RRAM process achieves a peak energy efficiency of 56.67 TOPS/W while demonstrating the eight-bitline hybrid CIM/digital MAC operation with 1–8-b i nputs and weights and 20-b outputs without quantization.