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An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling Timothy M. Hollis , Senior Member , IEEE, Ronny Schneider, Martin Brox , Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido
通过集成PAM-4技术，GDDR6X DRAM实现了单端信号传输下22Gbps的速率提升。
22 Gbps per-pin data rate
GDDR6XDRAMPAM-4单端信号高带宽
▸创新点1：集成四电平脉冲幅度调制（PAM-4）技术，通过单端内存接口实现高带宽传输，相比传统GDDR6的NRZ信号，PAM-4在相同带宽下将数据速率提升至22 Gb/s，显著提高了能效比。
▸创新点2：单端内存接口设计，通过优化信号路径和减少差分对的复杂性，降低了系统功耗和面积开销，同时保持了高数据速率和信号完整性。
▸创新点3：优化的时钟和数据路径设计，采用创新的时钟分配网络和数据同步技术，减少了时序偏差，确保了在22 Gb/s高数据速率下的稳定性和可靠性。
▸创新点4：组件封装设计的改进，通过创新的封装技术和材料选择，减少了信号损耗和串扰，进一步提升了整体系统的性能和能效。
Abstract
Demand for dynamic random access mem- ory (DRAM) bandwidth has outpaced DRAM transistor perfor- mance. Given the options of major process investment to scale beyond sixth-generation graphics double-data-rate (GDDR6) or replace GDDR6 with costly high bandwidth memory (HBM), this article presents a solution that simultaneously increases pin and energy efficiency through the integration of four-level pulse amplitude modulation (PAM-4) into the single-ended memory interface. Building upon the existing GDDR6 architecture, evo- lutionary modifications to input, output, clocking, and data path, along with the component package design, enable a per-pin data rate of more than 22 Gb/s.