← 返回 JSSC 论文列表JSSC 2022第1期Digital Circuits16nm
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET Colin Schmidt , John Wright , Student Member , IEEE, Zhongkai Wang, Student Member , IEEE, Eric Chang , Albert Ou , Student Member , IEEE
一款采用16nm FinFET工艺的八核144GHz RISC-V向量处理器SoC，集成可编程精度向量加速器。
16nm FinFET, 0.55V, 339MHz, 峰值能效209/92/56 GFLOPs/W (半/单/双精度)
RISC-V向量处理器SoC生成器设计能效优化
▸创新点1：基于生成器的设计方法学（方法创新） - 采用Chisel和BAG等生成器工具链，实现从数字到模拟模块的自动化生成，显著提升设计效率，支持125M门级规模的SoC集成。
▸创新点2：集成开源与定制化模块（系统创新） - 结合开源RISC-V核心与项目专用向量加速器，通过模块化设计实现灵活的功能扩展，验证了异构计算架构的可扩展性。
▸创新点3：可编程精度向量加速器（电路创新） - 支持从半精度到双精度的动态精度切换，在0.55V/339MHz下实现209-56 GFLOPs/W的能效比，突破传统固定精度加速器的能效瓶颈。
▸创新点4：16nm FinFET工艺下的高能效设计（工艺创新） - 通过电压缩放和频率优化，在先进工艺节点实现339MHz高频运行，同时保持亚瓦级功耗，为边缘计算提供硬件基础。
Abstract
This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator- based design methodology, which enables the integration of open-source and project-specific building blocks to develop dif- ferentiated functionality. The digital component generators use Chisel, the analog component generators use the Berkeley Analog Generator (BAG), and the physical design flow is implemented with Hammer. The chip totals 125 M gates and is implemented in a 16-nm finFET process. The vector accelerator achieves peak energy efficiency per task of 209 half-precision, 92 single- precision, and 56 double-precision GFLOPs/W for a matrix multiplication kernel at 0.55 V and 339 MHz.