← 返回 JSSC 论文列表JSSC 2022第2期Clocking & PLLs28nmCDRPAM-4
A 00285-mm2 068-pJbit Single-Loop Full-Rate Bang-Bang CDR Without Re ference and
本文提出了一种无需参考和独立频率检测器的单环路全速率Bang-Bang时钟数据恢复电路，支持PAM-4模式，具有宽频率捕获范围和高能效。
28nm CMOS, 23-to-29-Gb/s capture range, 0.68 pJ/bit energy efficiency
Bang-Bang时钟数据恢复PAM-4频率捕获能效CMOS
▸消除参考和独立频率检测器
▸通过时钟选择方案在BBPD曲线中添加固定采样点
▸混合控制电路实现宽频率范围的自动频率捕获
Abstract
This article reports a single-loop full-rate bang-bang
clock and data recovery (BBCDR) circuit supporting a four-
level pulse amplitude modulation (PAM-4) pattern. We eliminate
both the reference and the separate frequency detector (FD) by
deliberately adding two fixed strobe points in the bang-bang
phase detector (BBPD) curve via a clock-selection scheme.
As such, we can achieve a wide frequency-capture range in a
single-sided FD polarity. The BBPD also incorporates a hybrid
control circuit to a