← 返回 JSSC 论文列表JSSC 2022第2期Digital Circuits0.5-µmEqualizerNeural Network Accelerator
A 04-mA-Quiescent-Current 000091-THD N Class-D Audio Amplifier With Low-Complexit
提出一种低复杂度频率均衡技术，降低PWM残留混叠失真，实现低THD+N和低静态电流。
0.00091% THD+N, 0.0027% 最大THD+N, 168kHz fSW, 0.5-µm CMOS
Class-D音频放大器PWM残留混叠频率均衡THD+N静态电流
▸创新点1：低复杂度频率均衡技术（方法创新）：通过引入频率均衡路径，有效抑制PWM残余混叠失真，显著降低THD+N，同时保持低静态电流。
▸创新点2：最小化相位延迟（电路创新）：优化音频输入与环路滤波器输出之间的相位延迟，提升高频PWM开关分量的抵消能力，进一步降低THD+N。
▸创新点3：降低环路滤波器偏置电流（系统创新）：通过最小化相位延迟，减少环路滤波器第一级运算放大器的偏置电流需求，显著降低静态电流至0.4 mA。
▸创新点4：高性能指标（系统创新）：在168 kHz低开关频率下，实现0.00091%的最小THD+N和0.0027%的最大THD+N，同时达到2536的最高FOM。
Abstract
This article proposes a low-complexity frequency
equalization technique for pulsewidth modulation (PWM)-
residual-aliasing reduction in closed-loop Class-D audio ampli-
fiers to achieve both low total harmonic distortion plus noise
(THD+N) and low quiescent current. Based on the comprehen-
sive analysis on the phase shift delay between the audio input
and the loop filter’s output for the prior PWM-residual-aliasing
reduction technique, the proposed technique minimizes the
non-idealities via a freq