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JSSC 2022第2期RF & Wireless28nmLNANeural Network Accelerator

A 1.7–3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP 3 and 3.4–4.8 dB NF

一种基于开关、电容和升压变压器的N路径无源低噪声放大器,具有高线性、可调谐和高Q值特性。
28nm CMOS, 1.7-3.6 GHz, 20 MHz带宽, 9.8 dB电压增益, 3.4-4.8 dB NF, +23.5 dBm OB-IIP3, 33 dB HFRR3, +1.7 dBm B-1dB, 17.8-38.2 mW功耗
无源低噪声放大器N路径频率可调谐高线性谐波折叠抑制
使用开关、电容和升压变压器(SCT网络)构建高线性、频率可调谐和高Q值的带通响应
利用垂直耦合螺旋线圈的升压变压器实现通带中心与LO频率对齐及谐波折叠抑制
四路径设计在1.7-3.6 GHz范围内实现9.8 dB电压增益和3.4-4.8 dB噪声系数
Abstract
This article reports a channel-selection N-path passive low-noise amplifier (pLNA) featuring only switches, capacitors, and a step-up transformer (i.e. a SCT network) to build a highly linear, frequency-tunable, and high-Q band- pass response with in-band voltage gain and input-impedance matching. We also reveal the inductive and lowpass properties of the step-up transformer, composed of two vertically coupled spiral coils, for passband centering with the local oscillator (LO) frequency, and harmonic-folding reduction. Prototyped in 28 nm CMOS, a 4-path 20 MHz-bandwidth pLNA scores a 9.8 dB voltage gain and a 3.4–4.8 dB NF over a 1.7–3.6 GHz range. At 3 GHz, the out-of-band (OB)-IIP 3 measures +23.5 dBm, and the 3rd-harmonic-folding rejection ratio (HFRR 3)i s3 3d B .W i t h a blocker applied at the 80 MHz offset, the blocker −1d B compression point (B −1d B) attains +1.7 dBm, and the blocker N Fo n l yr a i s e sm o d e r a t e l yt o4 . 7d Bu pt oa0d B mb l o c k e r power. The only dynamic power comes from the four-phase 25%-duty-cycle LO generator that consumes 17.8–38.2 mW between 1.7 and 3.6 GHz. The entire pLNA occupies a 0.84 mm 2 die area.