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A Low-Jitter and Low-Spur Charge-Sampling PLL
提出一种低抖动和低杂散的电荷采样锁相环，采用新型电荷域子采样相位检测器。
40nm CMOS, 5mW, 11.2GHz, -77.3dBc, 48.6fs
低抖动低杂散电荷采样锁相环相位检测器
▸创新点1：电荷域子采样相位检测器（方法创新）。通过电荷域采样技术实现高相位检测增益，显著降低PLL带内相位噪声，无需传统功耗较高的隔离缓冲器，同时优化了VCO tank的调制电容。
▸创新点2：无功耗隔离缓冲器设计（电路创新）。通过最小化VCO tank的调制电容和降低采样时钟的占空比，有效抑制参考杂散，避免了传统设计中高功耗隔离缓冲器的使用。
▸创新点3：50µW RF无分频频率跟踪环路（系统创新）。在VCO面临突发频率干扰时，该低功耗环路能稳定锁定CSPLL，显著提升系统鲁棒性，功耗仅为50µW。
▸创新点4：低抖动与低杂散性能（性能创新）。在11.2 GHz下实现48.6 fs RMS抖动和-77.3 dBc参考杂散，功耗仅5 mW，综合性能优于同类设计。
Abstract
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the refer- ence spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- µW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm 2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW .