← 返回 JSSC 论文列表JSSC 2022第2期Memory65nmFlash MemoryCIM
An Embedded NAND Flash-Based Compute-In-Memory Array Demonstrated in a Standard
在65nm CMOS工艺中实验验证了基于嵌入式NAND闪存的存内计算阵列神经网络硬件。
98.5%手写数字识别准确率（与软件精度差距<0.5%）
存内计算NAND闪存神经网络硬件65nm CMOS突触权重存储
▸采用逻辑兼容的嵌入式闪存单元存储多级突触权重
▸使用位串行架构实现8位乘法累加运算
▸新型抗背模式编程验证方案将单元电流变化控制在0.6µA以内
Abstract
A neural network hardware inspired by the
3-D NAND flash array structure was experimentally demonstrated
in a standard 65-nm CMOS process. Logic-compatible embedded
flash memory cells were used for storing multi-level synaptic
weights while a bit-serial architecture enables 8 bit × 8b i t
multiply-and-accumulate operati on. A novel back-pattern toler-
ant program-verify scheme reduces the cell current variation
to less than 0.6 µA. Positive and negative weights are stored
in adjacent bitlines, gen