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JSSC 2022第2期Data Converters90nmDAC

An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs

提出一种低成本ISI加扰技术,结合DEM消除DAC中的非线性失真。
1-GS/s, 14-bit
电流舵DAC动态元件匹配符号间干扰非线性失真加扰技术
创新点1:提出了一种新型ISI加扰技术(方法创新),通过随机化电流源单元的切换顺序,将ISI引起的二阶非线性失真转化为不相关的噪声,从而显著降低DAC的非线性失真。
创新点2:将ISI加扰技术与动态元件匹配(DEM)相结合(系统创新),进一步提升了DAC的线性度,实验证明在1-GS/s、14-bit DAC中实现了与理论分析一致的性能。
创新点3:通过理论分析和实验验证(方法创新),证明了ISI加扰技术的有效性,测量结果显示输出功率谱与理论预测高度吻合,验证了技术的可行性。
创新点4:在90 nm CMOS工艺下实现了低成本的ISI加扰技术(电路创新),为高分辨率DAC设计提供了一种高效且易于集成的解决方案。
Abstract
The linearity of high-resolution current-steering digital-to-analog converters (DACs) is often limited by inter-symbol interference (ISI). While dynamic element matching (DEM) can be applied to convert a portion of the ISI to uncor- related noise instead of nonlinear distortion, DEM alone fails to prevent ISI from at least introducing strong second-order nonlin- ear distortion. This paper addresses this problem by proposing, analyzing, and experimentally demonstrating a low-cost add-on technique, called ISI scrambling, that, in conjunction with DEM, causes a DAC’s ISI to be free of nonlinear distortion. The ISI scrambling technique is demonstrated in a 1-GS/s, 14-bit DEM DAC implemented in 90 nm CMOS technology. The DAC’s measured linearity is in line with the state-of-the-art and its measured output power spectra closely match those predicted by this paper’s theoretical results.