Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold D

Abstract

This article presents a timing error detection and correction (EDaC) technique optimized for near-/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional hold constraints on monitored paths by instantaneously checking for late activity. Furthermore, two correction methods are discussed: a simple clock gating method and a low cycle overhead clock stretching method. Bot