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JSSC 2022第3期Clocking & PLLs180nm

A4 -μW Bandwidth/Power Scalable Delta–Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers

本文提出一种基于摆幅增强浮点逆变器的ΔΣ调制器,实现94.1dB动态范围和4µW功耗。
180nm CMOS, 4µW, 94.1dB动态范围, 89.3dB SNDR
ΔΣ调制器动态范围摆幅增强浮点逆变器功耗可扩展
全动态可扩展开关电容ΔΣ调制器
仅通过改变时钟频率实现功率和带宽可扩展
电容偏置和摆幅增强浮点逆变OTA
Abstract
This article presents a fully dynamic scalable switched-capacitor delta–sigma modulator that achieves a 94.1-dB dynamic range (DR). Power-and- bandwidth scalabil- ity by only changing the clock frequency is achieved using a capacitively biased and swing-enhanced floating inverter operational transconductance amplifier (OTA). Fabricated in a 180-nm CMOS process, the prototype achieves an signal-to- noise-and-distortion ratio (SNDR) of >87 dB across 4 × scaling from 100 to 400 kHz of the sampling frequency f S. At 200-kHz fS, it achieves an SNDR/DR of 89.3/94.1 dB while consuming 4 µW, leading to a DR-based Schreier figure of merit (FoM) of 177.1 dB.