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A 24 GHz-915 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Anjana D
一款高灵敏度2.4GHz唤醒接收器，采用包内占空比技术实现超低功耗。
2.4GHz, -91.5dBm灵敏度, 2μW@100ms延迟
唤醒接收器超低功耗包内占空比不确定中频CMOS集成
▸包内占空比技术降低空闲信道下的直流功耗
▸不确定中频拓扑结合PLL辅助事件驱动校准LO
▸信道嵌入式OOK方案实现确定性中频及抗干扰能力
Abstract
This article presents a highly integrated 2.4-GHz
wake-up receiver (WuRX) achieving 91.5 dBm sensitivity with
a state-of-the-art power an d latency combination of 2 µW
at 100 ms. The proposed within-packet duty-cycling method
employs a carrier-sense mechanism to turn off the WuRX early
under idle channel conditions, which reduces the dc-power com-
pared with conventional asynchronous packet-level duty cycling
by 9 × at 10 ms latency (21 µW) and 2 × at 1 s latency (0.9 µW)
at the cost of 2 dB in