A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver

Abstract

This article presents a highly integrated 2.4-GHz wake-up receiver (WuRX) achieving 91.5 dBm sensitivity with a state-of-the-art power an d latency combination of 2 µW at 100 ms. The proposed within-packet duty-cycling method employs a carrier-sense mechanism to turn off the WuRX early under idle channel conditions, which reduces the dc-power com- pared with conventional asynchronous packet-level duty cycling by 9 × at 10 ms latency (21 µW) and 2 × at 1 s latency (0.9 µW) at the cost of 2 dB in sensitivity. The uncertain-IF topology with a phase-locked loop (PLL)-a ided event-driven calibrated local-oscillator (LO) helps reduce the dc-power while maintaining a fast startup. The channel-embedded OOK scheme is used to create a deterministic IF to enable baseband (BB) channel selec- tion and achieve continuous wave (CW) interference tolerance of −47 dB at 20 MHz offset. Fabricated in 65 nm CMOS, input matching and LC oscillator are all implemented on-chip, and operation is demonstrated with integrated low dropout regulators to capture the degradations in realistic system integration.