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A 32-GHz 405 fs rms Jitter 2372d BF o MJIT Ring-Based Fractional-N Synthesizer A
提出了一种基于环形振荡器的低抖动数字分数-N频率合成器，采用频率倍增器和优化TDC等技术。
3.2-GHz输出时钟，96-MHz输入时钟，抖动306/405 fs，功耗11.7 mW
环形振荡器频率合成器时间-数字转换器数字-时间转换器低抖动
▸频率倍增器（FD）
▸优化的2位时间-数字转换器（TDC）
▸分段线性（PWL）校正的数字-时间转换器（DTC）
Abstract
A ring-oscillator (RO)-based low-jitter digital
fractional-N frequency synthesizer is presented. It employs a fre-
quency doubler (FD) that doubles the reference clock frequency,
a 2-bit time-to-digital converter (TDC) with optimized thresholds
to minimize the quantization error, and a high-resolution digital-
to-time converter (DTC) to cancel the quantization error of
the delta-sigma fractional divider (FDIV). DTC’s linearity is
improved using a piecewise linear (PWL) function-based cor-
rectio