JSSC 2022第3期RF & Wireless28nmCDRNeural Network Accelerator

An 1824-Gbs 093-pJbit Receiver With an Input-Level-Sensing CD R Using Clock-Embe

一种采用输入电平感知CDR的18.24Gb/s、0.93pJ/bit接收器

28nm CMOS, 1V供电, 18.24Gb/s, 0.93pJ/bit, 0.022mm²

接收器时钟数据恢复C-PHY接口低功耗电平感知

▸输入电平感知CDR电路消除传统C-PHY接收器的固有切换抖动

▸无参考电压或静态电流消耗的强信号检测技术

▸自动补偿模拟前端增益以适应工艺电压温度变化

Abstract

This article presents a receiver (RX) with an input- level-sensing clock and data recovery (CDR) circuit for a C-PHY interface with trio wires. The proposed CDR circuit detects a “strong” signal from the clock-embedded three-phase-coded signals and recovers the 3-bit wire state and clock simultaneously based on the detected “strong” signal without the inherent switching jitter of conventional C-PHY RXs. Also, the proposed input-level-sensing circuit allows for low power consumption and small siz