← 返回 JSSC 论文列表JSSC 2022第4期Data Converters16nmSAR ADCDAC
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
一种基于环形放大器的动态流水线-SAR ADC，采用背景校准技术实现高精度和低功耗。
16nm CMOS, 500 MS/s, 3.3 mW, 10.1 ENOB, 75.5-dB SFDR
流水线-SAR ADC环形放大器背景校准动态参考调节高精度
▸创新点1：新型SAR量化器（电路创新） - 采用创新的逐次逼近寄存器（SAR）量化器设计，显著提高了转换速度和精度，支持500 MS/s的高采样率，同时实现10.1 ENOB的高精度。
▸创新点2：窄带抖动注入技术（系统创新） - 通过窄带抖动注入技术实现了背景校准，有效校准了DAC失配、级间增益和环形放大器线性度，提升了整体系统的动态性能和稳定性。
▸创新点3：动态参考调节系统（电路创新） - 集成了全动态参考调节系统，能够在宽范围内动态调整参考电压，显著降低了功耗（3.3 mW）并提高了能效（62 fJ/conv-step）。
▸创新点4：环形放大器（ringamp）优化（电路创新） - 通过背景校准技术优化环形放大器的线性度和偏置，进一步提升了ADC的线性性能（75.5 dB SFDR）和能效。
Abstract
This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injec- tion to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Imple- mented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.