JSSC 2022第4期RF & Wireless7nm FinFETEqualizerPAM-4

A 124-pJb 112-Gbs 870 GbsMm Transceiver for In-Package Links in 7-nm FinFET Chi

7nm FinFET工艺下1.24pJ/b能效的112Gb/s PAM4收发器芯片设计

1.24pJ/b能效, 112Gb/s速率, <1e-12误码率

PAM4收发器芯片间互连连续时间线性均衡器注入锁定振荡器相位插值器

▸基于有源电感的单级CMOS连续时间线性均衡器(CTLE)

▸采用延迟型亚单位间隔两抽头FFE的电压模式发射机

▸基于注入锁定振荡器(ILO)的八相位时钟生成架构

Abstract

This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver supports 0–1.2-V i nput common mode and utilizes a single-stage active inductor-based CMOS continuous-time linear equalizer (CTLE) with 12 data slicers and two error slicers. The quad-rate voltage- mode transmitter implements d elay-based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC phase