A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET Chi Fung Poon , Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Daniel Zhaoyin Wu, Kee Hian Tan

Abstract

This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver supports 0–1.2-V i nput common mode and utilizes a single-stage active inductor-based CMOS continuous-time linear equalizer (CTLE) with 12 data slicers and two error slicers. The quad-rate voltage- mode transmitter implements d elay-based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC phase-locked loop (PLL) is distributed to eight transceiver channels. In each channel, an injection- locked oscillator (ILO) generates eight-phase clocks that feed an 8-bit CMOS phase interpolator (PI). The transceiver achieves <1e −12 bit error rate (BER) over 30-mm channel at 106.25 Gb/s and over 20-mm channel at 112 Gb/s.