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JSSC 2022第4期RF & Wireless22nm FD-SOIDAC

A mm-Wave Switched-Capacitor RFDAC Hieu Minh Nguyen Graduate Student Member IE

提出一种基于边缘组合器的毫米波开关电容RFDAC,通过时钟频率三倍提升实现高效Ka波段操作。
28 GHz Ka-band, 21 dBm Pout, >36% drain efficiency, >22% system efficiency, 2.4 Gb/s调制, 3.3% EVM, 30.8-dBc ACLR
毫米波开关电容RFDAC边缘组合器Ka波段
采用边缘组合器在输出级隐式三倍时钟频率
基于边缘组合的频率三倍延迟锁定环提升能效
新型布局结构应对大尺寸电容阵列的传输线效应
Abstract
This article proposes an interleaving switched- capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) opera- tion. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge- combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice o