A mm-Wave Switched-Capacitor RFDAC Hieu

Abstract

This article proposes an interleaving switched- capacitor RF digital-to-analog converter (RFDAC) using an edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable the mm-wave (mmW) opera- tion. Tripling in the output stage allows for increased energy efficiency, which is further improved by employing an edge- combining-based frequency-tripling delay-locked loop (DLL) in the clock generation network. The clock tripling is performed in each slice of the switched-capacitor PA (SCPA), which allows yet another 3× frequency reduction for the global clock distribution. Finally, a new layout structure accounts for transmission-line (TL) effects, due to the large physical size of the passive capacitor array. Implemented in 22-nm FD-SOI, the prototype achieves P out > 21 dBm, drain efficiency >36%, and system efficiency >22% while operating in the Ka-band at 28 GHz. Modulation at 2.4 Gb/s results in 3.3% EVM and 30.8-dBc adjacent channel leakage ratio (ACLR).