Abstract
We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4- µmp i t c h and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization tech- nique for CCO is introduced, which increases the maximum Manuscript received June 29, 2021; revised November 12, 2021; accepted December 23, 2021. Date of publication January 28, 2022; date of current version March 28, 2022. This article was approved by Guest Editor Borivoje Nikoli´ c. This work was supported by the IBM Research AI Hardware Center. The work of Riduan Khaddam-Aljameh, Geethan Karunaratne, and Abu Seba stian was supported by the European Research Council (ERC) through the European Union’s Horizon 2020 Research and Innovation Program under Grant 682675. (Corresponding authors: Riduan Khaddam-Aljameh; Abu Sebastian.) Riduan Khaddam-Aljameh, Milos Stani savljevic, and Evangelos Eleft- heriou were with IBM Research Europe, 8803 Rüschlikon, Switzer- land. They are now with Axelera AI, 8038 Zürich, Switzerland (e-mail: riduank@student.ethz.ch). Jordi Fornt Mas was with IBM Research Europe, 8803 Rüschlikon, Switzerland. He is now with the Barcelona Supercomputing Center, 08034 Barcelona, Spain. Geethan Karunaratne, Matthias Brä ndli, Urs Egger, S. R. Nandakumar, Manuel L