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JSSC 2022第4期Data Converters65nmSAR ADCVCO

OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR VCO ADC Sanjeev Tan

提出一种无OTA的1-1 MASH ADC,采用全被动噪声整形SAR VCO ADC结构,实现高能效转换。
0.16 mW功耗,71.5/75.8 dB SNDR/DR,1.1-MHz带宽,23.3 fJ/step Walden FoM
无OTA ADCMASH结构噪声整形SARVCO ADC被动电荷共享
采用全被动噪声整形SAR作为第一级,开环环形VCO作为第二级
利用被动电荷共享实现残差衰减以线性化VCO
提出低计算复杂度的前景级间增益校准算法
Abstract
We present an OTA-free 1-1 multi-stage noise- shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage- controlled oscillator (VCO) as the second stage. The key con- tribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuatio