← 返回 JSSC 论文列表JSSC 2022第5期Wireline I/O22nmPAM-4Neural Network Accelerator
A 128 Gbs 112 mW Single-Ended PAM4 Linear TIA With 27 μArms Input Noise in 22 nm
22nm FinFET CMOS工艺下实现的高能效128Gb/s单端PAM4线性TIA
22nm FinFET CMOS, 0.8V, 128Gb/s PAM4, 59.3dBΩ增益, 11.2mW功耗, 45.5GHz带宽, 27μArms输入噪声
跨阻放大器PAM4FinFET低功耗光接收机
▸基于CMOS反相器的并联反馈TIA设计
▸串联与并联电感峰化技术的带宽优化
▸低功耗高灵敏度线性TIA实现
Abstract
We review the design trade-offs that exist in
CMOS inverter-based shunt-feedback transimpedance amplifier
(SF-TIA) when optimizing for energy efficiency. We analyze the
performance of series and shunt inductive peaking techniques
for bandwidth enhancement and identify the most effective one
for low-power CMOS TIAs. As a design example, we present
a 128-Gb/s single-ended linear transimpedance amplifier (TIA)
intended for use in receivers for 400-G Ethernet optical modules
and co-packaged optics. The