JSSC 2022第5期RF & Wireless22nm FDSOI

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < −44-dBc HD3 Up To 1.5-V p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling

22nm FDSOI CMOS高线性度有源巴伦，实现44-dBc HD3和1.5V p-p输出摆幅

22nm FDSOI CMOS, 5V供电, 925mW功耗, <−44-dBc HD3, 1.5V p-p输出, 0.01-5.4GHz带宽

有源巴伦高线性度FDSOICMOS谐波失真

▸创新点1：采用高线性度基本模块(HLBB)（电路创新），通过强源极退化技术设计逆变器，显著提升基本模块的线性度，为整个系统提供高线性度基础。

▸创新点2：使用自举技术降低非线性（电路创新），通过自举技术有效抑制HLBB中的主导非线性机制，进一步优化线性度，适用于高电压摆幅应用。

▸创新点3：预失真技术消除输出级非线性（方法创新），通过预失真技术抵消输出驱动级的非线性，实现高达44-dBc的HD3性能，覆盖0.01–5.4 GHz带宽。

▸创新点4：PVT鲁棒性设计（系统创新），所有线性化技术均具备对工艺、电压和温度变化的鲁棒性，确保在实际应用中的稳定性和可靠性。

Abstract

In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. T o increase the linearity of this HLBB further , its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows < − 44-dBc third harmonic distortion (HD3) up to 1.5-V p-p output swing over 0.01–5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and ±5 ◦, respectively. The chip is powered from a 5-V supply and dissipates 925 mW.