← 返回 JSSC 论文列表JSSC 2022第5期RF & Wireless28nmSAR ADC
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP C
5G FR2频段功率放大器集成功率检测器，实现闭环EIRP控制
28nm CMOS SOI, 12.5dBm输出功率, 10% PAE, <-25dB EVM, 400MHz带宽
5G FR2功率放大器闭环控制CMOS SOI功率检测器
▸全集成功率检测路径，包括微型宽边定向耦合器和电流模式逐次逼近ADC
▸采用堆叠功率放大器设计，支持5G n257/n258/n261频段
▸功率检测器在15dB动态范围和85°C温度范围内误差小于±0.15dB
Abstract
A fifth-generation (5G) frequency range 2 (FR2)
transmitter front end with a fully integrated power detector
for enabling closed-loop power control is presented. The power
detection path includes a miniature broad-side directional cou-
pler, a sense pair, and a current-mode successive approximation
analog-to-digital converter. The stacked power amplifier (PA)
implemented in a 28-nm CMOS silicon on insulator (SOI) process
delivers 12.5-dBm output power with a power-added efficiency
of 10% and an err