A Sub-0.25-pJ/bit 47.6-to- 58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Xiaoteng Zhao , Student Member , IEEE

Abstract

This article reports a half-rate single-loop bang- bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input between 47.6 and 58.8 Gb/s. The core area is 0.056 mm 2. Both the achieved energy efficiency (0.22–0.25 pJ/bit) and the acquisition speed [9.8 (Gb/s)/ µs] compare favorably with the state of the art.