← 返回 JSSC 论文列表JSSC 2022第5期Clocking & PLLs28nmCDRPAM-4
A Sub-025-pJbit 476-to- 588-Gbs Reference-Less FD-Less Single-Loop PAM-4 Bang-Ba
一种无需参考和频率检测器的半速率单环路Bang-Bang时钟数据恢复电路，实现高速低功耗PAM-4信号处理。
28nm CMOS, 0.056mm²核心面积, 0.22–0.25 pJ/bit能效, 9.8 (Gb/s)/µs捕获速度
时钟数据恢复PAM-4Bang-Bang控制低功耗频率捕获
▸采用故意电流失配电荷泵对实现快速频率捕获
▸无需复杂高速数据或时钟路径
▸自动追踪47.6至58.8 Gb/s PAM-4输入
Abstract
This article reports a half-rate single-loop bang-
bang clock and data recovery (BBCDR) circuit without the
need of reference and frequency detector (FD). Specifically,
we propose a deliberate-current-mismatch charge-pump pair to
enable fast and robust frequency acquisition without identifying
the frequency error polarity. This technique eliminates the need
for a complex high-speed data or clock path during the frequency
acquisition, resulting in significant power savings. Prototyped
in 28-nm CMOS