A Sub-100 Fs RMS jitter 20 GHz Fractional- N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference Sachin Kalia , Salvatore Finocchiaro

Abstract

A 20-GHz fractional- N analog phase-locked loop (PLL) leveraging a novel high-speed charge pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable 2.5-GHz frequency reference using Texas Instrument’s indigenous bulk acoustic wave (BA W) resonator is demonstrated. The low noise high-frequency reference allows for significant lowering of the division modulus leading to enhanced suppression of CP, phase-frequency detector (PFD), and loop-filter (LF) noise. A low noise class-C transformer-coupled voltage-controlled oscillator (VCO) further allows for excellent jitter performance over wide integration bandwidths (BWs) while still working with a nominally low PLL loop BW. Capability is built into the design to characterize the PLL with either BA W or external reference. The design is implemented and fabricated in the GlobalFoundries 22-nm fully depleted silicon on insulator (FD-SOI) process. The class-C VCO is measured to be centered at ∼19.7 GHz with 16% tuning range (TR) while maintaining a flat |FOM|∼ 188 dBc/Hz (10-MHz offset) over the entire TR. The PLL measures an excellent jitter and |FOM j | of 65/92 fs and ∼249/245 dB in integer/fractional modes, respectively.