An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Co

Abstract

This article presents an inherent gain error- tolerant noise-shaping (NS) successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC). The architecture is hybrid with a pure passive-feedforward (FF) NS SAR ADC in the first stage of the pipeline, realizing an N-0 (2-0) multistage NS sigma–delta (MASH). The Nth order from the first stage shapes not only the quantization error and comparator noise but also the interstage gain and nonlinearity error, which greatly rela