A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS R. Gautam , Student Member , IEEE

Abstract

We present a low-power and low jitter two-stage 2.46–4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an 8 × clock multipli- cation with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first- stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo- differential ring oscillator embedded in a frequency tracking loop, thereby achieving a 64×–128× clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs rms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset- induced systematic jitter is calibrated, giving −53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fs rms at 4.92 GHz, −28.2-dBc reference spur, and 3-mW power consumption.