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A 129-to-151-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively
基于自适应算法的Bang-Bang相位检测器，实现129至151 GHz数字PLL，优化噪声整形。
28nm CMOS, 0.21 mm²核心面积, 69.5 fs rms抖动, 10.8 mW功耗
Bang-Bang相位检测器自适应算法噪声整形数字PLL高频段
▸自适应背景算法优化噪声整形
▸克服传统Bang-Bang相位检测器的噪声限制
▸实现高频段低抖动性能
Abstract
This work introduces a bang-bang fractional- N
phase-locked loop with quantization noise shaping that overcomes
the classical noise limit of a standard bang-bang phase detector.
An adaptive algorithm, working in the background of the
main system, guarantees optimal noise shaping across process
and environmental variations. The prototype, implemented in a
standard 28-nm CMOS process, has a core area of 0.21 mm
2 and
achieves an rms jitter (integrated from 1 kHz to 100 MHz) of
69.5 fs for integer-