A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device Y en-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang

Abstract

The development of security-aware mobile devices using wide-input–output (IO) nonvolatile memory (NVM) is hindered by high peak current, large area overhead for high read bandwidth (BWR), and considerable energy consumption for data movement between NVM and logic blocks. Furthermore, data stored in NVM are vulnerable to reverse-engineering attacks. This work presents a high BWR security-aware near- memory-computing spin-transfer torque magnetic random-access memory (STT-MRAM) macro usin g a multi-bit current-mode sense amplifier (MB-CSA) to reduce peak current and energy consumption for wide-IO access, a near-memory shift-and-rotate functionality (NSRF) in conjunc tion with the MB-CSA to reduce area overhead and enable the completion of read and logic operations within a single cycle, and a reverse-engineering-proof XOR -based memory data protector to protect data stored in NVM against reverse-engineering attacks. A 1-Mb 1024-b read STT-MRAM macro with data protector fabricated using foundry embedded 22-nm STT-MRAM. This work achieved 42.67 GB/s for BWR and 0.23 pJ/b. Inclusion of the NSRF circuit reduced area overhead by 33.3% while increasing latency by only 170 ps. Manuscript received May 8, 2021; revised August 9, 2021; accepted September 2, 2021. Date of publicatio n September 29, 2021; date of current version May 26, 2022. This article was approved by Associate Editor Vivek De. This work was supported in part by Taiwan Semiconductor Manufacturing Company (TSMC)-Joint Dev