← 返回 JSSC 论文列表JSSC 2022第6期Data Converters28nmPipeline ADC
A 33-GSs 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Zihao
一款采用线性化动态放大器的3.3GS/s 6位全动态流水线ADC
28nm CMOS, 3.3GS/s, 5.5mW, 40.02-fJ/conversion-step FoM
流水线ADC动态放大器高速转换低功耗设计片上校准
▸创新点1：后放大残差生成(PARG)方案 - 该方法创新性地将量化和放大操作并行化，显著提升了流水线ADC的速度，同时减少了硬件开销，实现了3.3 GS/s的高采样率。
▸创新点2：线性化动态放大器(DA) - 该电路创新通过线性化设计改善了动态放大器的性能，使得ADC在3.3 GS/s采样率下实现了34 dB的信号噪声失真比(SNDR)，提升了信号处理精度。
▸创新点3：片上校准技术 - 该系统创新通过共享校准硬件，实现了偏移和增益校准的片上集成，仅占用0.0166 mm²的面积，显著降低了功耗和面积开销，同时提高了ADC的稳定性和可靠性。
▸创新点4：硬件优化设计 - 该电路创新通过减少硬件数量（仅使用6个比较器和5个放大器），降低了校准开销，实现了全片上集成，进一步优化了功耗和面积，最终实现了40.02 fJ/conversion-step的Walden FoM。
Abstract
This article presents a single-channel 3.3-GS/s
6-b pipelined analog-to-digital converter (ADC), which features a
post-amplification residue generation (PARG) scheme, linearized
dynamic amplifier (DA), and on-chip calibration to achieve a high
speed, low power, and compact prototype. The PARG scheme
allows the quantization and amplification to run in parallel for a
fast pipelining operation. The 6-b ADC consists of six pipelined
stages with six comparators and five amplifiers in total. Such
a small n