A 5 Gb/s Time-Interleaved V oltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC Ji-Y

Abstract

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power con- sumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 2 7 − 1 pseudorandom binary sequence at 5 Gb/s.