JSSC 2022第6期RF & Wireless65nm

A 5 Gbs Time-Interleaved V oltage-Mode Duobinary Encoding Scheme for 3-D-Stacked

提出一种用于3D堆叠内存的低功耗双二进制编码方案，实现5Gb/s高速传输。

65nm CMOS, 5Gb/s, 0.373pJ/b/pF

双二进制编码电压模式驱动器3D堆叠决策反馈均衡器硅通孔

▸采用电压模式驱动器实现双二进制信号传输

▸设计小型编码器和边沿增强预驱动器以提高抗PVT变化能力

▸接收端使用单抽头DFE和简化NRZ转换电路降低硬件复杂度

Abstract

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power con- sumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, vo