A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for

Abstract

This article presents a 23.9–29.4 GHz digital LC-phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter out put after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM LC-digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The LC-PLL consumes 17.1 mW from a 0.8/1.0 V regulat