← 返回 JSSC 论文列表JSSC 2022第6期RF & Wireless10nm FinFETPLLPAM-4
A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tra
提出一种采用耦合倍频器的低相位噪声数字LC-PLL，用于224Gb/s PAM-4发射机时钟
23.9-29.4GHz, 65fs随机抖动, 17.1mW功耗, 0.8/1.0V供电
分数N分频数字锁相环耦合倍频器相位噪声优化PAM-4发射机频率跟踪环路
▸使用变压器耦合的14GHz和28GHz振荡器实现低相位噪声倍频
▸通过堆叠振荡器结构实现电流复用以降低功耗
▸集成频率跟踪环路(FTL)优化PVT变化下的相位噪声性能
Abstract
This article presents a 23.9–29.4 GHz digital
LC-phase-locked loop (PLL) architecture with a low phase noise
(PN) and power-efficient coupled frequency doubler for 224 Gb/s
PAM-4 transmitter clocking. The proposed frequency doubler is
designed with two oscillators running at 14 and 28 GHz which are
coupled by a transformer. Compared to a conventional frequency
doubler or a two-way coupled oscillator, the coupling between
the 14 and 28 GHz oscillators provides extra PN reduction as
the 14 GHz osci