A Fractional- N Digitally Intensive PLL Achieving 428-fs Jitter and <− 54-dBc Spurs Under 50-mV pp Supply Ripple Yu e C h e n, Student Member , IEEE, Jiang Gong , Student Member , IEEE

Abstract

In this article, we present a 4.5–5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capa- ble of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc–dc converter. Supply pushing of its inductor–capacitor ( LC ) oscil- lator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on-chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <−55-dBc fractional spur, and <−54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mV pp at 50-MHz reference divided by 3, 6, or 12.