← 返回 JSSC 论文列表JSSC 2022第6期Clocking & PLLs40nmPLLVCO
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Lo
一种基于环形振荡器的低抖动8GHz ADPLL，采用PVT鲁棒的模拟闭环设计
8GHz下289fs RMS抖动，1.1V供电，9.48mW功耗，0.055mm²面积
ADPLL低抖动环形振荡器电源噪声补偿PVT鲁棒性
▸创新点1：高增益模拟闭环电源噪声补偿(ACSC)：该方法创新通过引入高增益模拟闭环，显著提升了环形振荡器(RO)的频率稳定性，有效抑制了电源噪声对系统的影响，使系统在8 GHz频率下实现了289 fs的极低抖动。
▸创新点2：PVT鲁棒的复制配置：电路创新采用复制配置，使得系统在工艺、电压和温度(PVT)变化下仍能保持高性能，确保了系统的鲁棒性和可靠性，特别是在20 mV rms白噪声下，抖动仅为0.63 ps。
▸创新点3：噪声贡献综合分析：系统创新通过对ACSC噪声贡献的全面分析，优化了ADPLL的设计，进一步降低了输出抖动，提升了整体性能，同时保持了9.48 mW的低功耗和0.055 mm²的小面积。
▸创新点4：40-nm CMOS技术实现：采用先进的40-nm CMOS工艺，实现了高性能与低功耗的平衡，为高频低抖动ADPLL的设计提供了新的技术路径。
Abstract
This article presents a ring oscillator (RO)-based
all-digital phase-locked loop (ADPLL) that is implemented with
a high-gain analog closed loop for supply noise compensation
(ACSC). The ACSC not only allows high-frequency oscillation of
the RO but also is robust over process, voltage, and tempera-
ture (PVT) variations thanks to its replica-based configuration.
Moreover, a comprehensive analysis of the noise contribution of
the ACSC is conducted for the ADPLL to retain its low-jitter
output. Imp