A 0.5–1 V , −68 dB Power Supply Rejection Capacitorless Analog LDO Using V oltage-to-Time Conversion in 28-nm CMOS

Abstract

This article proposes an analog low-dropout (LDO) regulator using the voltage-to-time conversion technique to achieve high power-supply-rejection (PSR) at low supply voltages of less than 1 V . Integrating the time-domain signal into the current using a charge pump (CP) provides infinite dc gain, in principle, so that good regulation and high PSR can be achieved. Furthermore, a slew enhancement path using a time- converted signal is proposed to obtain a fast transient response even at low power supply voltages, and an auxiliary feedforward circuit has also been included to ensure wide load range stability. The proposed LDO designed to drive a 100-pF on-chip load capacitor and 150-mA load current was fabricated on a 28-nm CMOS process. The test measurement results show that the proposed LDO can operate in the 0.5–1-V i nput voltage range and achieved a high PSR of −52 to −68 dB at 1 kHz and −20 to −30 dB at 1 MHz, corresponding to the input voltage. Owing to the slew enhancement path, undershoot and overshoot were suppressed to 94 and 91 mV , respectively, for a 149-mA, 40-ns load current step.