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A 051 V 68 dB Power Supply Rejection Capacitorless Analog LDO Using V oltage-to
提出一种基于电压-时间转换技术的模拟LDO，在低于1V电源电压下实现高电源抑制比。
28nm CMOS, 0.5-1V, -68dB PSR@1kHz, 150mA负载
低压LDO电源抑制比电压时间转换电荷泵瞬态响应
▸采用电压-时间转换技术实现高PSR
▸集成电荷泵提供理论上无限直流增益
▸引入时间转换信号的斜率增强路径以提升瞬态响应
Abstract
This article proposes an analog low-dropout (LDO)
regulator using the voltage-to-time conversion technique to
achieve high power-supply-rejection (PSR) at low supply voltages
of less than 1 V . Integrating the time-domain signal into the
current using a charge pump (CP) provides infinite dc gain,
in principle, so that good regulation and high PSR can be
achieved. Furthermore, a slew enhancement path using a time-
converted signal is proposed to obtain a fast transient response
even at low power s