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A 52 Gbs Receiver for Next-Generation 8K Displays in 180 nm CMOS Process Tianyu
本文提出了一种用于下一代8K超高清电视的高速接收器，采用180nm CMOS工艺，支持5.2 Gb/s无差错通信。
180nm CMOS, 1.8V, 5.2 Gb/s, 29-dB通道损耗补偿, 120mA电流消耗
高速接收器8K超高清电视CMOS工艺连续时间线性均衡器决策反馈均衡器
▸电平转换被动连续时间线性均衡器
▸使用负电容扩展带宽的主动连续时间线性均衡器
▸带有下采样边缘采样路径的推测性决策反馈均衡器
Abstract
This article presents a high-speed receiver for next-
generation 8K ultra-high-definition TVs. The receiver supports
error-free communication between the timing controller and the
display driver integrated circuits (DDIs) across various channels.
Because the receiver must be co-integrated with pixel drivers in
the DDI, it must be implemented in a process with high-voltage
devices, which poses significant challenges in achieving beyond
5-Gb/s operation. We propose techniques for overcoming such
pro