STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse Jinshan Y ue , Member , IEEE, Y

Abstract

Computing-in-memory (CIM) is a promising architecture for energy-efficient neural network (NN) proces- sors. Several CIM macros have demonstrated high energy efficiency, while CIM-based system-on-a-chip is not well explored. This work presents a CIM NN processor, named STICKER-IM, which is implemented with sophisticated sys- tem integration. Three key innovations are proposed. First, a CIM-friendly block-wise sparsity (BWS) architecture is designed, enabling both activation-sparsity-aware acceleration and weight-sparsity-aware power-saving. Second, an adaptive kernel-/channel-order (KCO) mapping and intra-/inter-macro scheduling strategy is proposed to improve macro utiliza- tion and data reuse. Third, an efficient BWS-optimized CIM (BWS-CIM) macro with adaptive power- OFF ADCs is imple- mented. The STICKER-IM chip was fabricated in 65-nm CMOS technology. Experimental results show 5.8–158-TOPS/W average system energy efficiency on the sparse NN mod- els. The macro/system-level energy efficiency is 4.23 ×/3.06× higher compared with the sta te-of-the-art CIM macros and processors.