JSSC 2022第9期Memory40nmEmerging MemoryCIM

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control On-Chip Write-V e

40nm MLC-RRAM计算内存宏，支持稀疏控制和片上写验证，加速DNN推理。

40nm CMOS, 97.8 GOPS/mm², 44.5 TOPS/W

RRAM计算内存多级单元稀疏控制片上写验证

▸多级单元RRAM提升计算性能和密度

▸稀疏感知输入控制利用DNN模型的高激活稀疏性

▸片上写验证加速初始权重编程并补偿电阻漂移

Abstract

Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accel- erating deep neural network (DNN) inference. However, device characteristics, such as low-resistance values, susceptibility to drift, and single-level cells, may limit the capabilities of RRAM-based CIM. In addition, prior works generally used the off-chip write-verify scheme to tighten RRAM resistance distributions and used off-chip analog-to-digital converter (ADC) references for ﬁne-tuning