A 96.9-dB-Resolution 109- μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS Elisa Sacco , Student Member , IEEE, Johan V ergauwen, Member , IEEE

Abstract

This article presents a highly digital robust voltage-controlled oscillator (VCO)-based front end for multi- plexed single-ended resistive sensor readout applications. The architecture features a modified digital phase-locked loop (DPLL) structure that enables second-order noise shaping without any operational transconductance amplifiers (OTAs) and a single feedback digital-to-analog converter (DAC). The direct conver- sion of the sensor input resistance to time-domain information obviates the need for any conditioning circuit, thus resulting in a highly digital and area-compact architecture. The closed loop substantially reduces the amplitude of the signal at the VCO input, thereby achieving high linearity. To ensure high robustness against s upply and temperature variations, a double measurement approach is employed. Fabricated in a 180-nm CMOS process with a 0.1-mm 2 active area, the sensor readout consumes 109 µW of power and achieves a resolution of 96.9 dB for 0.5-ms conversion time, resulting in a Schreier figure of merit (FoM) of 166.5 dB. The circuit only requires a cheap and efficient single-point trimming calibration at room temperature. The low conversion time enables multiplexing among multiple sensor readouts. The supply and temperature sensitivities are 0.4 %/V and 36 ppm/ ◦C, respectively.