A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional- N Digital PLL Us

Abstract

This work presents a low-jitter and low-spur , fractional-N ring-oscillator-based digital phase-locked loop (RO-DPLL). First, to suppress fractional spurs, the probability- density-shaping delta–sigma modulator (PDS- /Delta1/Sigma1M) is presented. Since the output codes of the PDS- /Delta1/Sigma1M are designed to have a time-invariant probability density function (PDF), they have spur immunity to any nonlinearity (NL) of the digital-to-time converter (DTC). In addition, by using a special dither