An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based

Abstract

This work presents an ultra-low jitter , direct W - band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this W -band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the W -band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM -based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm 2. The rms jitter , integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the FoM JIT of –248.2 dB, which is the best among the state-of-the-art W -band frequency synthesizers.