W-band Scalable 2 × 2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication Huanbo Li ,J i x i nC h e n , Member , IEEE,D e b i nH o u , Member , IEEE

Abstract

This article presents a pair of W-band phased-array transmitter (TX) and receiver (RX) chipsets in a 0.13- μmS i G e BiCMOS process for high data-rate wireless communication. Both the chips integrate four compact front-end channels in 2 × 2 distribution, and the distance between the adjacent RF pads is less than 1.8 mm (0.56 λ at 90 GHz) to fit for the tight antenna array and enable array scaling by tiling multiple unit cells. A 6-bit active phase shifter based on the improved phase-inverting variable gain amplifiers is leveraged to achieve high phase- shift precision and bandwidth concurrently. A noise reduction technique using a parallel inductor to resonate with the parasitic capacitors of the cascode transistors is adopted in the low- noise amplifier design. A novel miniature power combiner, which occupies a much more compact area than the Wilkinson power combiner while delivering great RF performance, is proposed and elaborately analyzed. System-level calibration for local oscillator (LO) leakage and dc-offset suppression is enabled by introducing digitally controlled current sources into the up-conversion and down-conversion mixers. On-wafer measurements for the TX chip exhibit a single-channel IF-to-RF conversion gain (CG) of 26 dB, a competitively high output 1-dB compression point (OP 1d B) of 11 dBm. The RX chip achieves an RF-to-IF CG of 19.5 dB with 9-/14-GHz IF/RF 3-dB bandwidth, a noise figure of 7.7 dB, and an input 1-dB compression point of −28 dBm. The phase-shif