JSSC 2022第10期Power Management0.18-µm

A0 9 -μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive F

提出一种低静态电流高PSRR的LDO稳压器，采用电容前馈纹波消除技术。

0.18-µm CMOS, 0.9 µA静态电流, 200 mA最大负载电流, PSRR提升22 dB@1MHz

LDO稳压器电源抑制比静态电流电容前馈伪电阻偏置

▸创新点1：电容前馈纹波消除技术（CFFRC）通过引入前馈电容路径，有效抵消电源噪声，在1 MHz频率下实现PSRR提升22 dB，属于方法创新

▸创新点2：背靠背伪电阻偏置结构通过对称伪电阻设计降低静态电流至0.9 µA，同时维持高PSRR性能，属于电路架构创新

▸创新点3：全系统低静态电流设计（0.9 µA）在0.18 µm CMOS工艺下实现，通过优化偏置网络和反馈环路，兼顾200 mA大负载能力，属于系统级能效创新

▸创新点4：电容-电阻混合噪声抑制机制结合CFFRC与伪电阻，在宽频带（1 MHz）内实现电源噪声抑制，属于混合信号处理创新

Abstract

This article presents a high power supply rejection ratio (PSRR) low dropout (LDO) regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via feed-forward capacitors and back-to-back pseudo- resistors bias. This design was fabricated using the 0.18- µm CMOS technology. The entire proposed LDO consumes a qui- escent current of