A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer Dongsuk Kang, Student Member , IEEE, Jae-Woo Park , Student Member , IEEE, Injae Park, Student Member , IEEE,M i n - S uP a r k, Student Member , IEEE,X u e f a nJ i n, Member , IEEE, Kyu-Dong Hwang , Student Member , IEEE, Dae-Han Kwon

Abstract

In this article, we propose a duobinary trans- ceiver for graphics double-data-rate (GDDR) memory interfaces. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver (Rx) reduces the forwarded clock frequency and minimizes the capacitive loading of the front- end analog equalizer (EQ). To compensate for the channel loss, the transmitter is composed of a three-tap feed-forward EQ, and the Rx employs a continuous-time linear EQ. Also, an EQ adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a 10 −12 bit error rate at 21 Gb/s with 1.42 mW/Gb.