A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm 2 Density With Charge-Assisted Offset Cancellation Sense Amplifier Masaya Nakano , Y oshinobu Kaneda , Satoru Nakanishi, Y asumitsu Murai, Y osuke Tashiro, Y asuhiko Taito , Tomoya Ogawa, Hidenori Mitani, Takashi Ito, and

Abstract

With the expansion of Internet of Things (IoT) by artificial intelligence (AI), there is a strong demand for higher performance, higher intelligence, and lower cost in endpoint devices for crossover area located at the boundary between high-end micro controller unit (MCU) area and low-end micro processor unit (MPU) area, such as home automation, machine vision, robotics, and so on. This article presents a 40-nm embedded split-gate MONOS (SG-MONOS) flash macro with optimized memory array architecture and charge-assisted offset cancellation sense amplifier (CAOC-SA), which achieve high- speed random read operation of 200 MHz and high density of 7.91 Mb/mm 2 suitable for crossover devices.